CY2305SI-1H

 

 

Features

10-MHz to 100-/133-MHz operating range, compatible 

with CPU and PCI bus frequencies

• Zero input-output propagation delay

• Multiple low-skew outputs

— Output-output skew less than 250 ps

— Device-device skew less than 700 ps

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1 

(CY2309)

• Less than 200 ps cycle-cycle jitter, compatible with 

Pentium-based systems

• Test Mode to bypass phase-locked loop (PLL) (CY2309 

only [see “Select Input Decoding” on page 2])

• Available in space-saving 16-pin 150-mil SOIC or 

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil 

SOIC package (CY2305)

• 3.3V operation

• Industrial temperature available

 

 

 

**注意 & Noted:

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